Fundamentals of Digital Logic and Microcomputer Design
John Wiley & Sons, 8 Tem 2005 - 848 sayfa
Fundamentals of Digital Logic and Microcomputer Design, has long been hailed for its clear and simple presentation of the principles and basic tools required to design typical digital systems such as microcomputers. In this Fifth Edition, the author focuses on computer design at three levels: the device level, the logic level, and the system level. Basic topics are covered, such as number systems and Boolean algebra, combinational and sequential logic design, as well as more advanced subjects such as assembly language programming and microprocessor-based system design. Numerous examples are provided throughout the text.
Fundamentals of Digital Logic and Microcomputer Design is an essential reference that will provide you with the fundamental tools you need to design typical digital systems.
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4 COMBINATIONAL LOGIC DESIGN
5 SEQUENTIAL LOGIC DESIGN
6 MICROCOMPUTER ARCHITECTURE PROGRAMMING AND SYSTEM DESIGN CONCEPTS
7 DESIGN OF COMPUTER INSTRUCTION SET AND THE CPU
8 MEMORY IO AND PARALLEL PROCESSING
APPENDIX CMOTOROLA 68000 and SUPPORT CHIPS
APPENDIX D68000 EXECUTION TIMES
APPENDIX EINTEL 8086 AND SUPPORT CHIPS
APPENDIX F8086 INSTRUCTION SET REFERENCE DATA
APPENDIX G68000 INSTRUCTION SET
APPENDIX H8086 INSTRUCTION SET
9 INTEL 8086
10 MOTOROLA MC68000
11 INTEL AND MOTOROLA 32 64BIT MICROPROCESSORS
APPENDIX AANSWERS TO SELECTED PROBLEMS
Diğer baskılar - Tümünü görüntüle
16 bits 32 bits adder address register addressing mode arithmetic assembly language assembly language program binary number block Boolean bus cycle Bytes Coding Example cache chip complement conﬁgured contains contents data bus decimal decoder deﬁned device downto DTACK EPROM execution external ﬁeld ﬁgure ﬁrst ﬂip-ﬂop ﬂoating-point full adder function gate hardware implemented initial input instruction set integer Intel interface interrupt K-map load logic diagram main memory mem/reg memory address memory location microcomputer microprocessor microprogram minterms module operand operation output overﬂow Pentium perform pins pointer port PowerPC processor program counter provides reset result RISC segment register sequence sequential circuit shown in Figure signal signed speciﬁed stack status register STD_LOGIC std_logic_vector stored subroutine subtraction transistor truth table typical unsigned vector Verilog VHDL word Write zero
Sayfa 33 - NUL SOH STX ETX EOT ENQ ACK BEL BS HT LF VT FF CR SO SI OLE DC1 DC2 DC3 DC4 NAK SYN ETB CAN EM SUB ESC FS GS RS US...
Sayfa 420 - The request/grant pins are used by other local bus masters to force the processor to release the local bus at the end of the processor's current bus cycle. Each pin is bidirectional with RQ/GT0 having higher priority than RQ/GT,.
Sayfa 664 - D-10 indicates the number of clock periods required for the jump, lump-tosubroutine, load effective address, push effective address, and move multiple registers Instructions. The number of bus read and write cycles is shown In parenthesis as (r/w). Table D-10.
Sayfa 376 - Load effective address Load pointer using DS Load pointer using ES FLAG TRANSFER LAHF SAHF PUSHF POPF Load AH register from flags Store AH register in flags Push flags onto stack Pop flags off stack Table 2.2-1 Arithmetic Group.
Sayfa 429 - This functional configuration provides a means for communicating with a peripheral device or structure on a single 8-bit bus for both transmitting and receiving data (bidirectional bus I/O). "Handshaking" signals are provided to maintain proper bus flow discipline in a similar manner to MODE 1. Interrupt generation and enable/disable functions are also available. MODE 2 Basic Functional Definitions: • Used in Group A only. • One 8-bit, bi-directional bus Port (Port A) and a 5-bit control Port...
Sayfa 662 - D-6 indicates the number of clock periods for the single operand instructions. The number of bus read and write cycles is shown in parenthesis as (r/w). The number of clock periods and the number of read and write cycles must be added respectively to those of the effective address calculation where indicated. Table D-6.