Microprocessors: Theory and Applications (Intel and Motorola)Prentice Hall, 1992 - 468 sayfa |
Kitabın içinden
2 sonuçtan 1-2 arası sonuçlar
Sayfa 213
... stage pipeline is considered a reasonably optimal depth . With memory management , virtual memory tech- niques - traditionally a feature of mainframes - are also being used on the 32 - bit microprocessors . This allows programmers to ...
... stage pipeline is considered a reasonably optimal depth . With memory management , virtual memory tech- niques - traditionally a feature of mainframes - are also being used on the 32 - bit microprocessors . This allows programmers to ...
Sayfa 397
... stage outputs PA2 D2 PA1 D1 PAO Do INTA D7D6 D5 D4 D3 D2 D1 Do OE 0706050403020100 74LS244 OCTAL BUFFER WITH TRISTATE 17 16 15 14 13 12 11 10 Figure F - 21 SDK - 85 8703 schematic w ww w ww ww ww ww +5 V www RST6 OP code = F7 onto the ...
... stage outputs PA2 D2 PA1 D1 PAO Do INTA D7D6 D5 D4 D3 D2 D1 Do OE 0706050403020100 74LS244 OCTAL BUFFER WITH TRISTATE 17 16 15 14 13 12 11 10 Figure F - 21 SDK - 85 8703 schematic w ww w ww ww ww ww +5 V www RST6 OP code = F7 onto the ...
İçindekiler
MICROCOMPUTER ARCHITECTURE | 9 |
MICROCOMPUTER SOFTWARE | 49 |
Questions and Problems | 59 |
Telif Hakkı | |
15 diğer bölüm gösterilmiyor
Diğer baskılar - Tümünü görüntüle
Microprocessors: Theory and Applications (Intel and Motorola) Mohamed Rafiquzzaman Metin Parçacığı görünümü - 1992 |
Sık kullanılan terimler ve kelime öbekleri
16 bits 16-bit data A/D converter accumulator ADDRESS FIELD address register addressing mode assembly language binary buffer byte or word CALL CHARACTER chip circuit clock command contents coprocessor data bus data field data register data transfer decoding decremented digits disp8 display DMA controller DTACK enable EPROM example execution flags affected functions GPIB hardware hexadecimal HIGH I/O port index register input instruction set INTA Intel Corporation interface INTR jump keyboard latched loads logic low byte mem/reg memory address memory location memory-mapped I/O microcomputer microprocessor OP code operand operation output peripheral port 00 processor program counter register indirect RESET segment register service routine shown in Figure signal specified stack pointer status register stored subroutine TABLE tion typical vector voltage Write zero
Bu kitaba yapılan referanslar
Fundamentals of Digital Logic and Microcomputer Design Mohamed Rafiquzzaman Metin Parçacığı görünümü - 1999 |