High-performance Computer Architecture

algorithm architect architecture arithmetic unit bandwidth bitonic sorter bits bottleneck buffer cache memory cache misses cessors collision vector column Compare-and-Swap computer architecture concurrently continuum model Cosmic Cube cost datum delay diagonal disk efficient ENQUEUE equation evaluate example execution fetch Fetch-and-Add floating-point function hardware high-performance high-speed ILLIAC ILLIAC IV implementation increase initial input input/output instruction interconnection iteration loop machine main memory matrix memory system MSYPS multiplication multiprocessor N-set near-neighbor node number of processors obtain operands operation output overhead page faults parallel perfect shuffle performance permutation pipeline pipeline computers possible problem produce queue ratio recursive doubling reduced trace RISC segment semaphore sequence serial set associativity shared variable shift register shown in Fig shows single solution speedup stage structure synchronization tasks techniques Test-and-Set transient update vector processor virtual address virtual-memory