Microprocessors: Theory and Applications (Intel and Motorola)Prentice Hall, 1992 - 468 sayfa |
Kitabın içinden
54 sonuçtan 1-3 arası sonuçlar
Sayfa 207
... wait state , samples DTACK at the end of S6 , and , if recognized , latches data at the end of S8 ( 625 ns ) ; and the process continues . Since the 8 MHz ROM select +5 V D CLR a 19 Wait A state 01 D CLR a 10 Figure 6-25 Delay circuit ...
... wait state , samples DTACK at the end of S6 , and , if recognized , latches data at the end of S8 ( 625 ns ) ; and the process continues . Since the 8 MHz ROM select +5 V D CLR a 19 Wait A state 01 D CLR a 10 Figure 6-25 Delay circuit ...
Sayfa 334
... WAIT STATE 1357 ; 1358 IF WAITS 1359 IBTIM EQU 930 1368 OBTIM EQU 938 1361 TIM4 EQU 3720 1362 WAIT EQU 465 INTER - BIT DELAY OUTPUT INTER - BIT TIME DELAY 4 BIT TIME DELAY ¡ DELAY UNTIL READY TO SAMPLE BITS 1363 ENDIF 1364 ; 1365 ; 1366 ...
... WAIT STATE 1357 ; 1358 IF WAITS 1359 IBTIM EQU 930 1368 OBTIM EQU 938 1361 TIM4 EQU 3720 1362 WAIT EQU 465 INTER - BIT DELAY OUTPUT INTER - BIT TIME DELAY 4 BIT TIME DELAY ¡ DELAY UNTIL READY TO SAMPLE BITS 1363 ENDIF 1364 ; 1365 ; 1366 ...
Sayfa 339
... WAIT 859A CDF105 1762 CALL DELAY 059D C5 1763 PUSH B 059E 010800 1764 LXI 8,8 : GET INPUT BIT ; INTO CARRY WITH IT ; BRANCH IF NO START BIT : WAIT UNTIL MIDDLE OF BIT ; SAVE BC B < -- 0 , C < -- BITS TO RECEIVE 1765 C118 : 05A1 118C04 ...
... WAIT 859A CDF105 1762 CALL DELAY 059D C5 1763 PUSH B 059E 010800 1764 LXI 8,8 : GET INPUT BIT ; INTO CARRY WITH IT ; BRANCH IF NO START BIT : WAIT UNTIL MIDDLE OF BIT ; SAVE BC B < -- 0 , C < -- BITS TO RECEIVE 1765 C118 : 05A1 118C04 ...
İçindekiler
MICROCOMPUTER ARCHITECTURE | 9 |
MICROCOMPUTER SOFTWARE | 49 |
Questions and Problems | 59 |
Telif Hakkı | |
15 diğer bölüm gösterilmiyor
Sık kullanılan terimler ve kelime öbekleri
16 bits 16-bit data A/D converter accumulator ADDRESS FIELD address register addressing mode assembly language binary buffer byte or word CALL CHARACTER chip circuit clock command contents coprocessor data bus data field data register data transfer decoding decremented digits disp8 display DMA controller DTACK enable EPROM example execution flags affected functions GPIB hardware hexadecimal HIGH I/O port index register input instruction set INTA Intel Corporation interface INTR jump keyboard latched loads logic low byte mem/reg memory address memory location memory-mapped I/O microcomputer microprocessor OP code operand operation output peripheral port 00 processor program counter register indirect RESET segment register service routine shown in Figure signal specified stack pointer status register stored subroutine TABLE tion typical vector voltage Write zero
Bu kitaba yapılan referanslar
Fundamentals of Digital Logic and Microcomputer Design Mohamed Rafiquzzaman Metin Parçacığı görünümü - 1999 |