Microprocessors: Theory and Applications (Intel and Motorola)Prentice Hall, 1992 - 468 sayfa |
Kitabın içinden
58 sonuçtan 1-3 arası sonuçlar
Sayfa 125
... affected 8086 enters wait state XCHG mem , reg [ mem ] → [ reg ] XCHG reg , reg XLAT [ reg ] → [ reg ] [ AL ] ... affected with CF and OF cleared to zero ; mem uses DS as segment register reg and data can be 8- or 16 - bit ; no result ...
... affected 8086 enters wait state XCHG mem , reg [ mem ] → [ reg ] XCHG reg , reg XLAT [ reg ] → [ reg ] [ AL ] ... affected with CF and OF cleared to zero ; mem uses DS as segment register reg and data can be 8- or 16 - bit ; no result ...
Sayfa 433
... affected Segment register cannot be specified as reg ; data can be 8- or 16 - bit ; no flags affected Mem uses DS as segment reg- ister ; used for initializing CS , DS , ES , SS ; no flags affected Mem uses DS as segment reg- ister ; no ...
... affected Segment register cannot be specified as reg ; data can be 8- or 16 - bit ; no flags affected Mem uses DS as segment reg- ister ; used for initializing CS , DS , ES , SS ; no flags affected Mem uses DS as segment reg- ister ; no ...
Sayfa 441
... affected Memory Memory TEST CL , BL or or Register Register mem and reg can be 8- or 16 - bit ; segment registers not allowed ; no flags affected Mem uses DS as segment register ; no flags affected No memory - to- memory operation ...
... affected Memory Memory TEST CL , BL or or Register Register mem and reg can be 8- or 16 - bit ; segment registers not allowed ; no flags affected Mem uses DS as segment register ; no flags affected No memory - to- memory operation ...
İçindekiler
MICROCOMPUTER ARCHITECTURE | 9 |
MICROCOMPUTER SOFTWARE | 49 |
Questions and Problems | 59 |
Telif Hakkı | |
15 diğer bölüm gösterilmiyor
Sık kullanılan terimler ve kelime öbekleri
16 bits 16-bit data A/D converter accumulator ADDRESS FIELD address register addressing mode assembly language binary buffer byte or word CALL CHARACTER chip circuit clock command contents coprocessor data bus data field data register data transfer decoding decremented digits disp8 display DMA controller DTACK enable EPROM example execution flags affected functions GPIB hardware hexadecimal HIGH I/O port index register input instruction set INTA Intel Corporation interface INTR jump keyboard latched loads logic low byte mem/reg memory address memory location memory-mapped I/O microcomputer microprocessor OP code operand operation output peripheral port 00 processor program counter register indirect RESET segment register service routine shown in Figure signal specified stack pointer status register stored subroutine TABLE tion typical vector voltage Write zero
Bu kitaba yapılan referanslar
Fundamentals of Digital Logic and Microcomputer Design Mohamed Rafiquzzaman Metin Parçacığı görünümü - 1999 |