Fundamentals of Digital Logic and Microcomputer DesignRafi Systems, Incorporated, 1999 - 828 sayfa |
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28 sonuçtan 1-3 arası sonuçlar
Sayfa 374
... continues with execution of the CLR.W DO instruction . Suppose that the busy signal becomes HIGH , indicating the end of conversion during execution of the CLR.W DO instruction . This drives the INT signal to HIGH , interrupting the ...
... continues with execution of the CLR.W DO instruction . Suppose that the busy signal becomes HIGH , indicating the end of conversion during execution of the CLR.W DO instruction . This drives the INT signal to HIGH , interrupting the ...
Sayfa 444
... continues to output status information on the four A19 - A16 / S6 - S3 lines and will continue to output write data or input read data to or from the AD15 - AD 。 lines . CLK A19 / S6 , A6 / S3 T T 444 Fundamentals of Digital Logic and ...
... continues to output status information on the four A19 - A16 / S6 - S3 lines and will continue to output write data or input read data to or from the AD15 - AD 。 lines . CLK A19 / S6 , A6 / S3 T T 444 Fundamentals of Digital Logic and ...
Sayfa 523
... continue to execute other instructions until it reaches the speculative check operand . At this point , the microprocessor will check to see if the data it requested is ready . In this manner , the IA - 64 will be able to continue ...
... continue to execute other instructions until it reaches the speculative check operand . At this point , the microprocessor will check to see if the data it requested is ready . In this manner , the IA - 64 will be able to continue ...
İçindekiler
INTRODUCTION TO DIGITAL SYSTEMS | 1 |
NUMBER SYSTEMS AND CODES | 31 |
BOOLEAN ALGEBRA AND DIGITAL LOGIC GATES | 67 |
Telif Hakkı | |
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16 bits 32 bits adder address register addressing modes arithmetic assembly language assembly language program Assume binary number block Boolean bus cycle byte cache chip clock cycle complement consider contains contents control unit data bus decimal decoder digits display DSACK1 DTACK EPROM example execution flags flip-flop floating-point full adder function hardware hexadecimal implemented index register input instruction set integer Intel interface interrupt K-map latch loaded logic diagram m₁ main memory memory address memory location microcomputer microprocessor microprogram minterms Motorola MOVE.W multiplication offset on-chip op-code operand output Pentium perform physical address pins pipeline pointer port PowerPC processor program counter provides reset result RISC sequence sequential circuit shown in Figure signal specified stack stored subroutine synchronous transistor truth table typical unsigned vector word zero