Fundamentals of Digital Logic and Microcomputer DesignRafi Systems, Incorporated, 1999 - 828 sayfa |
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Sayfa 82
... active . A signal is disasserted when it is not at its active level . Active levels may be associated with inputs and outputs of logic gates . For example , an AND gate performs a logical AND operation on two active HIGH inputs and ...
... active . A signal is disasserted when it is not at its active level . Active levels may be associated with inputs and outputs of logic gates . For example , an AND gate performs a logical AND operation on two active HIGH inputs and ...
Sayfa 163
... active HIGH whereas NORS provide active LOW outputs . On the other hand , OR - NOR gates include both active HIGH and active LOW outputs . For example , the PAL16L8 is a 20 - pin chip with a maximum of 16 inputs , up to 8 outputs , one ...
... active HIGH whereas NORS provide active LOW outputs . On the other hand , OR - NOR gates include both active HIGH and active LOW outputs . For example , the PAL16L8 is a 20 - pin chip with a maximum of 16 inputs , up to 8 outputs , one ...
Sayfa 173
... active low inputs ( S and R ) will store a 1 ( Q = 1 and Q = 0 ) when the S input is activated by a low input ... active low signal can be defined as a signal that performs the desired function when it is low or 0. In Figure 5.2 , the SR ...
... active low inputs ( S and R ) will store a 1 ( Q = 1 and Q = 0 ) when the S input is activated by a low input ... active low signal can be defined as a signal that performs the desired function when it is low or 0. In Figure 5.2 , the SR ...
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INTRODUCTION TO DIGITAL SYSTEMS | 1 |
NUMBER SYSTEMS AND CODES | 31 |
BOOLEAN ALGEBRA AND DIGITAL LOGIC GATES | 67 |
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16 bits 32 bits adder address register addressing modes arithmetic assembly language assembly language program Assume binary number block Boolean bus cycle byte cache chip clock cycle complement consider contains contents control unit data bus decimal decoder digits display DSACK1 DTACK EPROM example execution flags flip-flop floating-point full adder function hardware hexadecimal implemented index register input instruction set integer Intel interface interrupt K-map latch loaded logic diagram m₁ main memory memory address memory location microcomputer microprocessor microprogram minterms Motorola MOVE.W multiplication offset on-chip op-code operand output Pentium perform physical address pins pipeline pointer port PowerPC processor program counter provides reset result RISC sequence sequential circuit shown in Figure signal specified stack stored subroutine synchronous transistor truth table typical unsigned vector word zero