Fundamentals of Digital Logic and Microcomputer DesignRafi Systems, Incorporated, 1999 - 828 sayfa |
Kitabın içinden
73 sonuçtan 1-3 arası sonuçlar
Sayfa 235
... added , that is , load 2010 into MAR . 2. Move the contents of this address to a data register , DO ; that is , move first data into DO . 3. Increment the MAR by 2 to hold 2012 , the address of the second data to be added . 4. Add the ...
... added , that is , load 2010 into MAR . 2. Move the contents of this address to a data register , DO ; that is , move first data into DO . 3. Increment the MAR by 2 to hold 2012 , the address of the second data to be added . 4. Add the ...
Sayfa 311
... added . First , the unit digits are added , producing a sum of 3 and a carry digit of 2. Similarly , the tens digits are added , producing a sum digit of 6 and a carry digit of 1. Because there is no carry propagation from the unit ...
... added . First , the unit digits are added , producing a sum of 3 and a carry digit of 2. Similarly , the tens digits are added , producing a sum digit of 6 and a carry digit of 1. Because there is no carry propagation from the unit ...
Sayfa 757
... added using several carry - save adders . This concept can be extended to design an n x n pipelined multiplier . Here n partial products must be summed with 2n bits per partial product . So , as n increases , the hardware cost ...
... added using several carry - save adders . This concept can be extended to design an n x n pipelined multiplier . Here n partial products must be summed with 2n bits per partial product . So , as n increases , the hardware cost ...
İçindekiler
INTRODUCTION TO DIGITAL SYSTEMS | 1 |
NUMBER SYSTEMS AND CODES | 31 |
BOOLEAN ALGEBRA AND DIGITAL LOGIC GATES | 67 |
Telif Hakkı | |
13 diğer bölüm gösterilmiyor
Sık kullanılan terimler ve kelime öbekleri
16 bits 32 bits adder address register addressing modes arithmetic assembly language assembly language program Assume binary number block Boolean bus cycle byte cache chip clock cycle complement consider contains contents control unit data bus decimal decoder digits display DSACK1 DTACK EPROM example execution flags flip-flop floating-point full adder function hardware hexadecimal implemented index register input instruction set integer Intel interface interrupt K-map latch loaded logic diagram m₁ main memory memory address memory location microcomputer microprocessor microprogram minterms Motorola MOVE.W multiplication offset on-chip op-code operand output Pentium perform physical address pins pipeline pointer port PowerPC processor program counter provides reset result RISC sequence sequential circuit shown in Figure signal specified stack stored subroutine synchronous transistor truth table typical unsigned vector word zero