Fundamentals of Digital Logic and Microcomputer DesignRafi Systems, Incorporated, 1999 - 828 sayfa |
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16 sonuçtan 1-3 arası sonuçlar
Sayfa 82
... asserted , the output is asserted . 3.5 Boolean Algebra Boolean algebra provides basis for logic operations using binary variables . Alphabetic charac- ters are used to represent the binary variables . A binary variable can have either ...
... asserted , the output is asserted . 3.5 Boolean Algebra Boolean algebra provides basis for logic operations using binary variables . Alphabetic charac- ters are used to represent the binary variables . A binary variable can have either ...
Sayfa 508
... asserted LOW , the 80386 latches or reads data . Until READY # pin is asserted LOW by the external device , the 80386 inserts wait states . One must ensure that the data is ready before READY # is asserted . The BS16 # is connected to ...
... asserted LOW , the 80386 latches or reads data . Until READY # pin is asserted LOW by the external device , the 80386 inserts wait states . One must ensure that the data is ready before READY # is asserted . The BS16 # is connected to ...
Sayfa 594
... asserted ( LOW ) by the memory devices at the end of S4 . A simplified schematic showing an interface of a 68000 to ... assert DTACK . From the 68000 timing diagram of Figure 10.13 , AS goes to LOW after approxi- mately two cycles ( 500 ...
... asserted ( LOW ) by the memory devices at the end of S4 . A simplified schematic showing an interface of a 68000 to ... assert DTACK . From the 68000 timing diagram of Figure 10.13 , AS goes to LOW after approxi- mately two cycles ( 500 ...
İçindekiler
INTRODUCTION TO DIGITAL SYSTEMS | 1 |
NUMBER SYSTEMS AND CODES | 31 |
BOOLEAN ALGEBRA AND DIGITAL LOGIC GATES | 67 |
Telif Hakkı | |
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Sık kullanılan terimler ve kelime öbekleri
16 bits 32 bits adder address register addressing modes arithmetic assembly language assembly language program Assume binary number block Boolean bus cycle byte cache chip clock cycle complement consider contains contents control unit data bus decimal decoder digits display DSACK1 DTACK EPROM example execution flags flip-flop floating-point full adder function hardware hexadecimal implemented index register input instruction set integer Intel interface interrupt K-map latch loaded logic diagram m₁ main memory memory address memory location microcomputer microprocessor microprogram minterms Motorola MOVE.W multiplication offset on-chip op-code operand output Pentium perform physical address pins pipeline pointer port PowerPC processor program counter provides reset result RISC sequence sequential circuit shown in Figure signal specified stack stored subroutine synchronous transistor truth table typical unsigned vector word zero