Fundamentals of Digital Logic and Microcomputer DesignRafi Systems, Incorporated, 1999 - 828 sayfa |
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39 sonuçtan 1-3 arası sonuçlar
Sayfa 63
... bit micro- processor , and the high - order 8 - bit subtraction can be obtained by using SBB ( SUBTRACT with borrow ) ... added in such a way that after its inclusion , the number of I's in the message together with the parity bit is an even ...
... bit micro- processor , and the high - order 8 - bit subtraction can be obtained by using SBB ( SUBTRACT with borrow ) ... added in such a way that after its inclusion , the number of I's in the message together with the parity bit is an even ...
Sayfa 137
... added for bit 0 of the two numbers . On the other hand , addition of three bits ( two bits of the two numbers and a previous carry , which may be 0 or 1 ) is required for all the subsequent bits . Note that two half - adders are ...
... added for bit 0 of the two numbers . On the other hand , addition of three bits ( two bits of the two numbers and a previous carry , which may be 0 or 1 ) is required for all the subsequent bits . Note that two half - adders are ...
Sayfa 404
... bit number 002016 can be added with the 8 - bit number E116 by sign- extending El as follows : 0020 16 Sign ... bits . CWD sign - extends the AX register into the DX register . That is , if the most significant bit of AX is 1 , then ...
... bit number 002016 can be added with the 8 - bit number E116 by sign- extending El as follows : 0020 16 Sign ... bits . CWD sign - extends the AX register into the DX register . That is , if the most significant bit of AX is 1 , then ...
İçindekiler
INTRODUCTION TO DIGITAL SYSTEMS | 1 |
NUMBER SYSTEMS AND CODES | 31 |
BOOLEAN ALGEBRA AND DIGITAL LOGIC GATES | 67 |
Telif Hakkı | |
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16 bits 32 bits adder address register addressing modes arithmetic assembly language assembly language program Assume binary number block Boolean bus cycle byte cache chip clock cycle complement consider contains contents control unit data bus decimal decoder digits display DSACK1 DTACK EPROM example execution flags flip-flop floating-point full adder function hardware hexadecimal implemented index register input instruction set integer Intel interface interrupt K-map latch loaded logic diagram m₁ main memory memory address memory location microcomputer microprocessor microprogram minterms Motorola MOVE.W multiplication offset on-chip op-code operand output Pentium perform physical address pins pipeline pointer port PowerPC processor program counter provides reset result RISC sequence sequential circuit shown in Figure signal specified stack stored subroutine synchronous transistor truth table typical unsigned vector word zero