Fundamentals of Digital Logic and Microcomputer DesignRafi Systems, Incorporated, 1999 - 828 sayfa |
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Sayfa 361
... cache rather than reading them repeatedly from the external main memory . Thus , the performance is greatly improved . For example , an on - chip cache memory is implemented in Intel's 32 - bit microprocessor , the 80486 / Pentium , and ...
... cache rather than reading them repeatedly from the external main memory . Thus , the performance is greatly improved . For example , an on - chip cache memory is implemented in Intel's 32 - bit microprocessor , the 80486 / Pentium , and ...
Sayfa 362
... Cache Memory Address = 8 bits Data = 16 bits FIGURE 8.12 Addresses for main memory and cache memory The relationship between the cache and main memory blocks is established using mapping techniques . Three widely used mapping techniques ...
... Cache Memory Address = 8 bits Data = 16 bits FIGURE 8.12 Addresses for main memory and cache memory The relationship between the cache and main memory blocks is established using mapping techniques . Three widely used mapping techniques ...
Sayfa 728
... cache is shown in Figure 11.19 . If an instruction fetch occurs when the cache is enabled , the cache is first checked to determine if the word requested is in the cache . This is achieved by first using 6 bits of the memory address ...
... cache is shown in Figure 11.19 . If an instruction fetch occurs when the cache is enabled , the cache is first checked to determine if the word requested is in the cache . This is achieved by first using 6 bits of the memory address ...
İçindekiler
INTRODUCTION TO DIGITAL SYSTEMS | 1 |
NUMBER SYSTEMS AND CODES | 31 |
BOOLEAN ALGEBRA AND DIGITAL LOGIC GATES | 67 |
Telif Hakkı | |
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16 bits 32 bits adder address register addressing modes arithmetic assembly language assembly language program Assume binary number block Boolean bus cycle byte cache chip clock cycle complement consider contains contents control unit data bus decimal decoder digits display DSACK1 DTACK EPROM example execution flags flip-flop floating-point full adder function hardware hexadecimal implemented index register input instruction set integer Intel interface interrupt K-map latch loaded logic diagram m₁ main memory memory address memory location microcomputer microprocessor microprogram minterms Motorola MOVE.W multiplication offset on-chip op-code operand output Pentium perform physical address pins pipeline pointer port PowerPC processor program counter provides reset result RISC sequence sequential circuit shown in Figure signal specified stack stored subroutine synchronous transistor truth table typical unsigned vector word zero