Fundamentals of Digital Logic and Microcomputer DesignRafi Systems, Incorporated, 1999 - 828 sayfa |
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Sayfa 232
... Clock Signals The system clock signals are contained in the control bus . These signals generate the appropri- ate clock periods during which instruction executions are carried out by the microprocessor . The clock signals vary from one ...
... Clock Signals The system clock signals are contained in the control bus . These signals generate the appropri- ate clock periods during which instruction executions are carried out by the microprocessor . The clock signals vary from one ...
Sayfa 331
... clock pulse . The controller moves to state T1 with this clock pulse . When the controller is in T2 , R ← R + M and Q ← Q - 1 are performed . All these operations take place at the trailing edge of the next clock pulse . The ...
... clock pulse . The controller moves to state T1 with this clock pulse . When the controller is in T2 , R ← R + M and Q ← Q - 1 are performed . All these operations take place at the trailing edge of the next clock pulse . The ...
Sayfa 755
... clock , segment 2 is busy with Tl while segment S1 is busy with T2 . Continuing in this manner , the task Tl is completed at the end of the fourth clock . However , following this point , one task is shipped out per clock . This is the ...
... clock , segment 2 is busy with Tl while segment S1 is busy with T2 . Continuing in this manner , the task Tl is completed at the end of the fourth clock . However , following this point , one task is shipped out per clock . This is the ...
İçindekiler
INTRODUCTION TO DIGITAL SYSTEMS | 1 |
NUMBER SYSTEMS AND CODES | 31 |
BOOLEAN ALGEBRA AND DIGITAL LOGIC GATES | 67 |
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16 bits 32 bits adder address register addressing modes arithmetic assembly language assembly language program Assume binary number block Boolean bus cycle byte cache chip clock cycle complement consider contains contents control unit data bus decimal decoder digits display DSACK1 DTACK EPROM example execution flags flip-flop floating-point full adder function hardware hexadecimal implemented index register input instruction set integer Intel interface interrupt K-map latch loaded logic diagram m₁ main memory memory address memory location microcomputer microprocessor microprogram minterms Motorola MOVE.W multiplication offset on-chip op-code operand output Pentium perform physical address pins pipeline pointer port PowerPC processor program counter provides reset result RISC sequence sequential circuit shown in Figure signal specified stack stored subroutine synchronous transistor truth table typical unsigned vector word zero