Fundamentals of Digital Logic and Microcomputer DesignRafi Systems, Incorporated, 1999 - 828 sayfa |
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66 sonuçtan 1-3 arası sonuçlar
Sayfa 144
... enable inputs to control the circuit operation . An example of the commercial decoder is the 74HC138 or the 74LS138 . This is a 3 - to - 8 decoder with three enable lines G1 , G24 , and G2B . When G1 = H , G24 = L and G2B = L , the ...
... enable inputs to control the circuit operation . An example of the commercial decoder is the 74HC138 or the 74LS138 . This is a 3 - to - 8 decoder with three enable lines G1 , G24 , and G2B . When G1 = H , G24 = L and G2B = L , the ...
Sayfa 374
... ENABLE . This HIGHOUTPUT ENABLE is required to disable the A / D's output . The microcomputer continues with execution of the CLR.W DO instruction . Suppose that the busy signal becomes HIGH , indicating the end of conversion during ...
... ENABLE . This HIGHOUTPUT ENABLE is required to disable the A / D's output . The microcomputer continues with execution of the CLR.W DO instruction . Suppose that the busy signal becomes HIGH , indicating the end of conversion during ...
Sayfa 473
... Enable integer display OUT PORTA , AL MOV AL , DL OR AL , 10H AND OUT IRET AL , 1FH PORTA , AL Enable fractional display Display fractional part Return from interrupt Display integer part Move fractional part Disable integer display ...
... Enable integer display OUT PORTA , AL MOV AL , DL OR AL , 10H AND OUT IRET AL , 1FH PORTA , AL Enable fractional display Display fractional part Return from interrupt Display integer part Move fractional part Disable integer display ...
İçindekiler
INTRODUCTION TO DIGITAL SYSTEMS | 1 |
NUMBER SYSTEMS AND CODES | 31 |
BOOLEAN ALGEBRA AND DIGITAL LOGIC GATES | 67 |
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16 bits 32 bits adder address register addressing modes arithmetic assembly language assembly language program Assume binary number block Boolean bus cycle byte cache chip clock cycle complement consider contains contents control unit data bus decimal decoder digits display DSACK1 DTACK EPROM example execution flags flip-flop floating-point full adder function hardware hexadecimal implemented index register input instruction set integer Intel interface interrupt K-map latch loaded logic diagram m₁ main memory memory address memory location microcomputer microprocessor microprogram minterms Motorola MOVE.W multiplication offset on-chip op-code operand output Pentium perform physical address pins pipeline pointer port PowerPC processor program counter provides reset result RISC sequence sequential circuit shown in Figure signal specified stack stored subroutine synchronous transistor truth table typical unsigned vector word zero