Fundamentals of Digital Logic and Microcomputer DesignRafi Systems, Incorporated, 1999 - 828 sayfa |
Kitabın içinden
42 sonuçtan 1-3 arası sonuçlar
Sayfa 362
... fields , an index field and a tag field . Because the cache address is 8 bits wide ( 28 = 256 ) , the low - order 8 bits of the microprocessor's address form the index field , and the remaining 4 bits constitute the tag field . This is ...
... fields , an index field and a tag field . Because the cache address is 8 bits wide ( 28 = 256 ) , the low - order 8 bits of the microprocessor's address form the index field , and the remaining 4 bits constitute the tag field . This is ...
Sayfa 649
... Field MSB → N , Z = 1 if all bits in field are zero ; Z = 0 otherwise O's → Field Notation BFTST ( EA ) { offset : width } BFCLR ( EA ) BFCLR 1-32 BFSET 1-32 l's Field BFCHG 1-32 Field → Field BFEXTS 1-32 Field → Dn ; sign ...
... Field MSB → N , Z = 1 if all bits in field are zero ; Z = 0 otherwise O's → Field Notation BFTST ( EA ) { offset : width } BFCLR ( EA ) BFCLR 1-32 BFSET 1-32 l's Field BFCHG 1-32 Field → Field BFEXTS 1-32 Field → Dn ; sign ...
Sayfa 710
... field can be removed from the microinstruction format . Therefore , the control function field is used to specify the branch address itself . Typically , each microinstruction will have two fields , as shown next : CONDITION- SELECT FIELD ...
... field can be removed from the microinstruction format . Therefore , the control function field is used to specify the branch address itself . Typically , each microinstruction will have two fields , as shown next : CONDITION- SELECT FIELD ...
İçindekiler
INTRODUCTION TO DIGITAL SYSTEMS | 1 |
NUMBER SYSTEMS AND CODES | 31 |
BOOLEAN ALGEBRA AND DIGITAL LOGIC GATES | 67 |
Telif Hakkı | |
13 diğer bölüm gösterilmiyor
Sık kullanılan terimler ve kelime öbekleri
16 bits 32 bits adder address register addressing modes arithmetic assembly language assembly language program Assume binary number block Boolean bus cycle byte cache chip clock cycle complement consider contains contents control unit data bus decimal decoder digits display DSACK1 DTACK EPROM example execution flags flip-flop floating-point full adder function hardware hexadecimal implemented index register input instruction set integer Intel interface interrupt K-map latch loaded logic diagram m₁ main memory memory address memory location microcomputer microprocessor microprogram minterms Motorola MOVE.W multiplication offset on-chip op-code operand output Pentium perform physical address pins pipeline pointer port PowerPC processor program counter provides reset result RISC sequence sequential circuit shown in Figure signal specified stack stored subroutine synchronous transistor truth table typical unsigned vector word zero