Fundamentals of Digital Logic and Microcomputer DesignRafi Systems, Incorporated, 1999 - 828 sayfa |
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Sayfa 13
... hand , some TTL families define the logic levels in the active mode operation of the transistor and are called nonsaturated logic . Since the transistors do not go into saturation , these families do not have any saturation delay time ...
... hand , some TTL families define the logic levels in the active mode operation of the transistor and are called nonsaturated logic . Since the transistors do not go into saturation , these families do not have any saturation delay time ...
Sayfa 32
... hand side of Equation 2.4 corresponds to Equation 2.2 . The right - hand side of Equation 2.4 is in the form of Equation 2.1 , where b = 10 , d1 = 5 , d2 = 3 , d3 = 2 , q = 3 , p = 0 , dp1 = ... = do = 0 . Finally , consider the mixed ...
... hand side of Equation 2.4 corresponds to Equation 2.2 . The right - hand side of Equation 2.4 is in the form of Equation 2.1 , where b = 10 , d1 = 5 , d2 = 3 , d3 = 2 , q = 3 , p = 0 , dp1 = ... = do = 0 . Finally , consider the mixed ...
Sayfa 218
... hand , if A = 1 , the circuit increments register X by 1 and then moves to the next state , T2 . Note that the following opera- tions are performed by the circuit during state To : 1. Clear register X. 2. Check flip - flop A for 1 or 0 ...
... hand , if A = 1 , the circuit increments register X by 1 and then moves to the next state , T2 . Note that the following opera- tions are performed by the circuit during state To : 1. Clear register X. 2. Check flip - flop A for 1 or 0 ...
İçindekiler
INTRODUCTION TO DIGITAL SYSTEMS | 1 |
NUMBER SYSTEMS AND CODES | 31 |
BOOLEAN ALGEBRA AND DIGITAL LOGIC GATES | 67 |
Telif Hakkı | |
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16 bits 32 bits adder address register addressing modes arithmetic assembly language assembly language program Assume binary number block Boolean bus cycle byte cache chip clock cycle complement consider contains contents control unit data bus decimal decoder digits display DSACK1 DTACK EPROM example execution flags flip-flop floating-point full adder function hardware hexadecimal implemented index register input instruction set integer Intel interface interrupt K-map latch loaded logic diagram m₁ main memory memory address memory location microcomputer microprocessor microprogram minterms Motorola MOVE.W multiplication offset on-chip op-code operand output Pentium perform physical address pins pipeline pointer port PowerPC processor program counter provides reset result RISC sequence sequential circuit shown in Figure signal specified stack stored subroutine synchronous transistor truth table typical unsigned vector word zero