Fundamentals of Digital Logic and Microcomputer DesignRafi Systems, Incorporated, 1999 - 828 sayfa |
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Sayfa 180
... input of the master flip- flop ( FF # 1 ) is 1 and the CLK input = 1 ( leading edge ) . The output of the inverter will apply a O at the CLK input of the slave flip - flop ( FF # 2 ) . Thus , FF # 2 is disabled . The master flip - flop ...
... input of the master flip- flop ( FF # 1 ) is 1 and the CLK input = 1 ( leading edge ) . The output of the inverter will apply a O at the CLK input of the slave flip - flop ( FF # 2 ) . Thus , FF # 2 is disabled . The master flip - flop ...
Sayfa 368
... input or output bits . Each port can be configured as an input or output port by another register called the " command " or “ data - direction register . " The port contains the actual input or output data . The data - direction ...
... input or output bits . Each port can be configured as an input or output port by another register called the " command " or “ data - direction register . " The port contains the actual input or output data . The data - direction ...
Sayfa 441
... input . A Schmitt trigger is a special analog circuit that shifts the switching threshold based on whether the input changes from LOW to HIGH or from HIGH to LOW . To illustrate this , consider a TTL Schmitt trigger inverter . Suppose ...
... input . A Schmitt trigger is a special analog circuit that shifts the switching threshold based on whether the input changes from LOW to HIGH or from HIGH to LOW . To illustrate this , consider a TTL Schmitt trigger inverter . Suppose ...
İçindekiler
INTRODUCTION TO DIGITAL SYSTEMS | 1 |
NUMBER SYSTEMS AND CODES | 31 |
BOOLEAN ALGEBRA AND DIGITAL LOGIC GATES | 67 |
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16 bits 32 bits adder address register addressing modes arithmetic assembly language assembly language program Assume binary number block Boolean bus cycle byte cache chip clock cycle complement consider contains contents control unit data bus decimal decoder digits display DSACK1 DTACK EPROM example execution flags flip-flop floating-point full adder function hardware hexadecimal implemented index register input instruction set integer Intel interface interrupt K-map latch loaded logic diagram m₁ main memory memory address memory location microcomputer microprocessor microprogram minterms Motorola MOVE.W multiplication offset on-chip op-code operand output Pentium perform physical address pins pipeline pointer port PowerPC processor program counter provides reset result RISC sequence sequential circuit shown in Figure signal specified stack stored subroutine synchronous transistor truth table typical unsigned vector word zero