Fundamentals of Digital Logic and Microcomputer DesignRafi Systems, Incorporated, 1999 - 828 sayfa |
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Sayfa 351
... lines and the two control lines described so far are unidirec- tional in nature ; that is , in these lines information always travels from the processor to external units . Also , in Figure 8.1 eight bidirectional data lines D , through ...
... lines and the two control lines described so far are unidirec- tional in nature ; that is , in these lines information always travels from the processor to external units . Also , in Figure 8.1 eight bidirectional data lines D , through ...
Sayfa 381
... lines lines HOLD INT Data lines Data lines Data HLDA lines RW HOLD RW CS INT HLDA RS DMA Request DMA ACK Addres Bus Data Bus HOLD HLDA RW INT 1/0 device Data lines FIGURE 8.24 Typical block transfer Because block - transfer DMA is ...
... lines lines HOLD INT Data lines Data lines Data HLDA lines RW HOLD RW CS INT HLDA RS DMA Request DMA ACK Addres Bus Data Bus HOLD HLDA RW INT 1/0 device Data lines FIGURE 8.24 Typical block transfer Because block - transfer DMA is ...
Sayfa 584
... lines , DMA using the HALT line will not normally be used . The HALT pin can also be used as an output signal . The ... Lines IPLO , IPL1 , and IPL2 are the three interrupt control lines These lines provide for seven inter- rupt priority ...
... lines , DMA using the HALT line will not normally be used . The HALT pin can also be used as an output signal . The ... Lines IPLO , IPL1 , and IPL2 are the three interrupt control lines These lines provide for seven inter- rupt priority ...
İçindekiler
INTRODUCTION TO DIGITAL SYSTEMS | 1 |
NUMBER SYSTEMS AND CODES | 31 |
BOOLEAN ALGEBRA AND DIGITAL LOGIC GATES | 67 |
Telif Hakkı | |
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16 bits 32 bits adder address register addressing modes arithmetic assembly language assembly language program Assume binary number block Boolean bus cycle byte cache chip clock cycle complement consider contains contents control unit data bus decimal decoder digits display DSACK1 DTACK EPROM example execution flags flip-flop floating-point full adder function hardware hexadecimal implemented index register input instruction set integer Intel interface interrupt K-map latch loaded logic diagram m₁ main memory memory address memory location microcomputer microprocessor microprogram minterms Motorola MOVE.W multiplication offset on-chip op-code operand output Pentium perform physical address pins pipeline pointer port PowerPC processor program counter provides reset result RISC sequence sequential circuit shown in Figure signal specified stack stored subroutine synchronous transistor truth table typical unsigned vector word zero