Fundamentals of Digital Logic and Microcomputer DesignRafi Systems, Incorporated, 1999 - 828 sayfa |
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47 sonuçtan 1-3 arası sonuçlar
Sayfa 329
... processing section by establishing the necessary control inputs . Figure 7.35 shows the detailed logic diagram of the processing section , along with the control inputs . inbus 4 Co : Ro C1 : Minbus LC1 C2 : Qinbus M R C3 : F = r + 1 C1 ...
... processing section by establishing the necessary control inputs . Figure 7.35 shows the detailed logic diagram of the processing section , along with the control inputs . inbus 4 Co : Ro C1 : Minbus LC1 C2 : Qinbus M R C3 : F = r + 1 C1 ...
Sayfa 485
... processing . " Fetching , decoding , execution , memory management , and bus access for several instructions are ... Processing Modes The 80386 has three processing modes : Intel 16- , 32- , and 64 - Bit Microprocessors 485.
... processing . " Fetching , decoding , execution , memory management , and bus access for several instructions are ... Processing Modes The 80386 has three processing modes : Intel 16- , 32- , and 64 - Bit Microprocessors 485.
Sayfa 765
... processing elements . Each processing element has its own small local memory unit . The operation of all the processing elements is under the control of a central control unit ( CCU ) . Typically , the CCU reads an instruction from the ...
... processing elements . Each processing element has its own small local memory unit . The operation of all the processing elements is under the control of a central control unit ( CCU ) . Typically , the CCU reads an instruction from the ...
İçindekiler
INTRODUCTION TO DIGITAL SYSTEMS | 1 |
NUMBER SYSTEMS AND CODES | 31 |
BOOLEAN ALGEBRA AND DIGITAL LOGIC GATES | 67 |
Telif Hakkı | |
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16 bits 32 bits adder address register addressing modes arithmetic assembly language assembly language program Assume binary number block Boolean bus cycle byte cache chip clock cycle complement consider contains contents control unit data bus decimal decoder digits display DSACK1 DTACK EPROM example execution flags flip-flop floating-point full adder function hardware hexadecimal implemented index register input instruction set integer Intel interface interrupt K-map latch loaded logic diagram m₁ main memory memory address memory location microcomputer microprocessor microprogram minterms Motorola MOVE.W multiplication offset on-chip op-code operand output Pentium perform physical address pins pipeline pointer port PowerPC processor program counter provides reset result RISC sequence sequential circuit shown in Figure signal specified stack stored subroutine synchronous transistor truth table typical unsigned vector word zero