Fundamentals of Digital Logic and Microcomputer DesignRafi Systems, Incorporated, 1999 - 828 sayfa |
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Sayfa 58
... result is incorrect . Four bits are too small to hold the correct answer . If we increase the number of bits for A and B to 5 , the correct result can be obtained as follows : = A = -610 110102 B = +410001002 A = Add 2's complement of B ...
... result is incorrect . Four bits are too small to hold the correct answer . If we increase the number of bits for A and B to 5 , the correct result can be obtained as follows : = A = -610 110102 B = +410001002 A = Add 2's complement of B ...
Sayfa 242
... result is zero , and it is reset to 0 if the result is nonzero . A parity flag is set to 1 to indicate whether the result of the last operation contains either an even number of 1's ( even parity ) or an odd number of 1's ( odd parity ) ...
... result is zero , and it is reset to 0 if the result is nonzero . A parity flag is set to 1 to indicate whether the result of the last operation contains either an even number of 1's ( even parity ) or an odd number of 1's ( odd parity ) ...
Sayfa 405
... result can be adjusted to provide the correct unpacked BCD using the AAA instruction as follows : ADD CL , DL [ CL ] = 3216 = ACSII for 2 [ DL ] = 3516 = ASCII for 5 Result [ CL ] = 6716 Move ASCII result adjusts only [ AL ] MOV AL , CL ...
... result can be adjusted to provide the correct unpacked BCD using the AAA instruction as follows : ADD CL , DL [ CL ] = 3216 = ACSII for 2 [ DL ] = 3516 = ASCII for 5 Result [ CL ] = 6716 Move ASCII result adjusts only [ AL ] MOV AL , CL ...
İçindekiler
INTRODUCTION TO DIGITAL SYSTEMS | 1 |
NUMBER SYSTEMS AND CODES | 31 |
BOOLEAN ALGEBRA AND DIGITAL LOGIC GATES | 67 |
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16 bits 32 bits adder address register addressing modes arithmetic assembly language assembly language program Assume binary number block Boolean bus cycle byte cache chip clock cycle complement consider contains contents control unit data bus decimal decoder digits display DSACK1 DTACK EPROM example execution flags flip-flop floating-point full adder function hardware hexadecimal implemented index register input instruction set integer Intel interface interrupt K-map latch loaded logic diagram m₁ main memory memory address memory location microcomputer microprocessor microprogram minterms Motorola MOVE.W multiplication offset on-chip op-code operand output Pentium perform physical address pins pipeline pointer port PowerPC processor program counter provides reset result RISC sequence sequential circuit shown in Figure signal specified stack stored subroutine synchronous transistor truth table typical unsigned vector word zero