Fundamentals of Digital Logic and Microcomputer DesignRafi Systems, Incorporated, 1999 - 828 sayfa |
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88 sonuçtan 1-3 arası sonuçlar
Sayfa 98
... shows the K - map for three variables . Figure 3.29 ( a ) shows a map with three liter- als in each square . There are eight minterms ( mo , mɩ , ... , m7 ) for three variables . Figure 3.29 ( b ) shows these minterms - one for each ...
... shows the K - map for three variables . Figure 3.29 ( a ) shows a map with three liter- als in each square . There are eight minterms ( mo , mɩ , ... , m7 ) for three variables . Figure 3.29 ( b ) shows these minterms - one for each ...
Sayfa 136
... shows a block diagram of the half- adder . Table 4.5 shows the truth table of the half - adder . TABLE 4.5 Truth Table of the Half - Adder Inputs Outputs Decimal x y C S Value 0 0 0 0 0 0 1 0 1 1 1 0 0 1 1 1 1 1 0 2 From the truth table ...
... shows a block diagram of the half- adder . Table 4.5 shows the truth table of the half - adder . TABLE 4.5 Truth Table of the Half - Adder Inputs Outputs Decimal x y C S Value 0 0 0 0 0 0 1 0 1 1 1 0 0 1 1 1 1 1 0 2 From the truth table ...
Sayfa 251
... shows the transfer of the result from the adder to the data bus . Finally , Figure 6.24 shows the transfer of the data bus contents to the register . Arithmetic and Logic unit ( ALU ) Status flags Shifter Complementer Boolean Logic and ...
... shows the transfer of the result from the adder to the data bus . Finally , Figure 6.24 shows the transfer of the data bus contents to the register . Arithmetic and Logic unit ( ALU ) Status flags Shifter Complementer Boolean Logic and ...
İçindekiler
INTRODUCTION TO DIGITAL SYSTEMS | 1 |
NUMBER SYSTEMS AND CODES | 31 |
BOOLEAN ALGEBRA AND DIGITAL LOGIC GATES | 67 |
Telif Hakkı | |
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16 bits 32 bits adder address register addressing modes arithmetic assembly language assembly language program Assume binary number block Boolean bus cycle byte cache chip clock cycle complement consider contains contents control unit data bus decimal decoder digits display DSACK1 DTACK EPROM example execution flags flip-flop floating-point full adder function hardware hexadecimal implemented index register input instruction set integer Intel interface interrupt K-map latch loaded logic diagram m₁ main memory memory address memory location microcomputer microprocessor microprogram minterms Motorola MOVE.W multiplication offset on-chip op-code operand output Pentium perform physical address pins pipeline pointer port PowerPC processor program counter provides reset result RISC sequence sequential circuit shown in Figure signal specified stack stored subroutine synchronous transistor truth table typical unsigned vector word zero