Fundamentals of Digital Logic and Microcomputer DesignRafi Systems, Incorporated, 1999 - 828 sayfa |
Kitabın içinden
74 sonuçtan 1-3 arası sonuçlar
Sayfa 497
... specified register . The instruction loads 16 bits into DS ( for LDS ) or into ES ( for LES ) . The other register loaded is 32 bits for 32 - bit operand size and 16 bits for 16 - bit operand size . The 16- and 32 - bit registers to be ...
... specified register . The instruction loads 16 bits into DS ( for LDS ) or into ES ( for LES ) . The other register loaded is 32 bits for 32 - bit operand size and 16 bits for 16 - bit operand size . The 16- and 32 - bit registers to be ...
Sayfa 547
... Specified registers are transferred to or from consecutive memory locations starting at the location specified by the effective address . Two ( W ) or four ( L ) bytes of data are transferred between a data regis- ter and alternate ...
... Specified registers are transferred to or from consecutive memory locations starting at the location specified by the effective address . Two ( W ) or four ( L ) bytes of data are transferred between a data regis- ter and alternate ...
Sayfa 680
... specified by bit number BI is true ( The condition " true " is specified by a value in BO ) . For example , bc 12,0 , target means that branch with offset target if the condi- tion specified by bit 0 in CR ( BI = 0 indicates the result ...
... specified by bit number BI is true ( The condition " true " is specified by a value in BO ) . For example , bc 12,0 , target means that branch with offset target if the condi- tion specified by bit 0 in CR ( BI = 0 indicates the result ...
İçindekiler
INTRODUCTION TO DIGITAL SYSTEMS | 1 |
NUMBER SYSTEMS AND CODES | 31 |
BOOLEAN ALGEBRA AND DIGITAL LOGIC GATES | 67 |
Telif Hakkı | |
13 diğer bölüm gösterilmiyor
Sık kullanılan terimler ve kelime öbekleri
16 bits 32 bits adder address register addressing modes arithmetic assembly language assembly language program Assume binary number block Boolean bus cycle byte cache chip clock cycle complement consider contains contents control unit data bus decimal decoder digits display DSACK1 DTACK EPROM example execution flags flip-flop floating-point full adder function hardware hexadecimal implemented index register input instruction set integer Intel interface interrupt K-map latch loaded logic diagram m₁ main memory memory address memory location microcomputer microprocessor microprogram minterms Motorola MOVE.W multiplication offset on-chip op-code operand output Pentium perform physical address pins pipeline pointer port PowerPC processor program counter provides reset result RISC sequence sequential circuit shown in Figure signal specified stack stored subroutine synchronous transistor truth table typical unsigned vector word zero